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Ultralow Power, 1.8 V, 3 mm x 3 mm, 2-Channel Capacitance Converter AD7156
FEATURES
Ultralow power Power supply voltage: 1.8 V to 3.6 V Operation power supply current: 70 A typical Power-down current: 2 A typical Fast response time Conversion time: 10 ms per channel Wake-up time from serial interface: 300 s Adaptive environmental compensation 2 capacitance input channels Sensor capacitance (CSENS): 0 pF up to 13 pF Sensitivity up to 3 fF 2 modes of operation Standalone with fixed settings Interfaced to a microcontroller for user-defined settings 2 detection output flags 2-wire serial interface (I2C-compatible) Operating temperature: -40C to +85C 10-lead LFCSP package (3 mm x 3 mm x 0.8 mm)
GENERAL DESCRIPTION
The AD7156 delivers a complete signal processing solution for capacitive sensors, featuring an ultralow power converter with fast response time. The AD7156 uses an Analog Devices, Inc., capacitance-todigital converter (CDC) technology, which combines features important for interfacing to real sensors, such as high input sensitivity and high tolerance of both input parasitic ground capacitance and leakage current. The integrated adaptive threshold algorithm compensates for any variations in the sensor capacitance due to environmental factors like humidity and temperature or due to changes in the dielectric material over time. By default, the AD7156 operates in standalone mode using the fixed power-up settings and indicates detection on two digital outputs. Alternatively, the AD7156 can be interfaced to a microcontroller via the serial interface, the internal registers can be programmed with user-defined settings, and the data and status can be read from the part. The AD7156 operates with a 1.8 V to 3.6 V power supply. It is specified over the temperature range of -40C to +85C.
APPLICATIONS
Buttons and switches Proximity sensing Contactless switching Position detection Level detection Portable products
FUNCTIONAL BLOCK DIAGRAM
VDD CIN1 CSENS1 EXC1 MUX CIN2 CSENS2 EXC2 EXCITATION THRESHOLD - CDC DIGITAL FILTER SERIAL INTERFACE
SCL SDA
AD7156
THRESHOLD
OUT1
OUT2
07726-001
GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
AD7156 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 11 Capacitance-to-Digital Converter ............................................ 11 CAPDAC ..................................................................................... 11 Comparator and Threshold Modes .......................................... 12 Adaptive Threshold .................................................................... 12 Sensitivity..................................................................................... 12 Data Average ............................................................................... 13 Hysteresis ..................................................................................... 13 Timeout........................................................................................ 13 Auto-DAC Adjustment .............................................................. 14 Power-Down Timer ................................................................... 14 Register Descriptions ..................................................................... 15 Status Register ............................................................................. 16 Data Registers ............................................................................. 17 Average Registers ........................................................................ 18 Fixed Threshold Registers ......................................................... 18 Sensitivity Registers ................................................................... 18 Timeout Registers....................................................................... 18 Setup Registers ............................................................................ 19 Configuration Register .............................................................. 20 Power-Down Timer Register .................................................... 21 CAPDAC Registers .................................................................... 21 Serial Number Register.............................................................. 21 Chip ID Register ......................................................................... 21 Serial Interface ................................................................................ 22 Read Operation........................................................................... 22 Write Operation.......................................................................... 22 AD7156 Reset ............................................................................. 23 General Call ................................................................................ 23 Hardware Design Considerations ................................................ 24 Overview ..................................................................................... 24 Parasitic Capacitance to Ground .............................................. 24 Parasitic Resistance to Ground ................................................. 24 Parasitic Parallel Resistance ...................................................... 24 Parasitic Serial Resistance ......................................................... 25 Input Overvoltage Protection ................................................... 25 Input EMC Protection ............................................................... 25 Power Supply Decoupling and Filtering.................................. 25 Application Examples ................................................................ 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27
REVISION HISTORY
10/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD7156 SPECIFICATIONS
VDD = 1.8 V to 3.6 V, GND = 0 V, temperature range = -40C to +85C, unless otherwise noted. Table 1.
Parameter CAPACITIVE INPUT Conversion Input Range, CIN to EXC 2, 3 Min 3.2 1.6 0.8 0.4 Typ 4 2 1 0.5 2.0 1.6 1.4 1.0 50 10 50 -20 0.5 -2 50 5 0.05 60 4 10 12.5 200 0.25 75 VDD/2 16 1000 1 0.4 VDD - 0.6 70 0.1 6 25 5 +2 +20 Max Unit 1 pF pF pF pF fF fF fF fF pF M k % %FSR % fF fF % dB fF/V pF fF LSB % of CIN range V kHz pF M V V % of VDD % of VDD A pF V A ISINK = -6.0 mA VOUT = VDD Test Conditions/Comments 4 pF input range 2 pF input range 1 pF input range 0.5 pF input range 4 pF input range 2 pF input range 1 pF input range 0.5 pF input range See Figure 4, Figure 5, and Figure 6 See Figure 10 and Figure 11 See Figure 14 See Figure 17 CIN and EXC pins disconnected CIN and EXC pins disconnected See Figure 16
Resolution 4, 5
Maximum Allowed Capacitance, CIN to GND4, 6 Minimum Allowed Resistance, CIN to GND4, 6 Maximum Allowed Serial Resistance4, 6 Gain Error Gain Deviation over Temperature4 Gain Matching Between Ranges4 Offset Error4 Offset Deviation over Temperature4 Integral Nonlinearity (INL)4 Channel-to-Channel Isolation4 Power Supply Rejection4 CAPDAC Full Range Resolution (LSB)4 Differential Nonlinearity (DNL)4 Auto-DAC Increment/Decrement4, 7 EXCITATION Voltage4, 7 Frequency Maximum Allowed Capacitance EXC to GND4, 6 Minimum Allowed Resistance EXC to GND4, 6 LOGIC OUTPUTS (OUT1, OUT2) Output Low Voltage (VOL) Output High Voltage (VOH) SERIAL INTERFACE INPUTS (SCL, SDA) Input High Voltage (VIH) Input Low Voltage (VIL) Input Leakage Current Input Pin Capacitance OPEN-DRAIN OUTPUT (SDA) Output Low Voltage (VOL) Output High Leakage Current (IOH)
25
See Figure 18 See Figure 7, Figure 8, and Figure 9 See Figure 12 and Figure 13 ISINK = -3 mA ISOURCE = +3 mA
0.4 0.1 5
Rev. 0 | Page 3 of 28
AD7156
Parameter POWER REQUIREMENTS VDD-to-GND Voltage IDD Current4, 8 IDD Current Power-Down Mode4, 8 Min 1.8 65 70 2 2 Typ Max 3.6 75 85 10 17 Unit 1 V A A A A Test Conditions/Comments
VDD 2.7 V, see Figure 20 VDD = 3.6 V, see Figure 20 VDD 2.7 V, see Figure 21 VDD = 3.6 V, see Figure 21
1 2
Capacitance units: 1 pF = 1 x 10-12 F; 1 fF = 10-15 F. The CAPDAC can be used to shift (offset) the input range. The total capacitance of the sensor can therefore be up to the sum of the CAPDAC value and the conversion input range. With the auto-DAC feature, the CAPDAC is adjusted automatically when the CDC input value is lower than 25% or higher than 75% of the CDC nominal input range. 3 The maximum capacitance of the sensor connected between the EXCx and CINx pins is equal to the sum of the minimum guaranteed value of the CAPDAC and the minimum guaranteed input range. 4 The maximum specification is not production tested but is supported by characterization data at initial product release. 5 The resolution of the converter is not limited by the output data format or output data LSB (least significant bit) size, but by the converter and system noise level. The noise-free resolution is defined as level of peak-to-peak noise coming from the converter itself, with no connection to the CIN and EXC pins. 6 These specifications are understood separately. Any combination of the capacitance to ground and serial resistance may result in additional errors, for example gain error, gain drift, offset error, offset drift, and power supply rejection. 7 Specification is not production tested but is guaranteed by design. 8 Digital inputs equal to VDD or GND.
Rev. 0 | Page 4 of 28
AD7156
TIMING SPECIFICATIONS
VDD = 1.8 V to 3.6 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = VDD, temperature range = -40C to +85C, unless otherwise noted. Table 2.
Parameter CONVERTER Conversion Time 1 Wake-Up Time from Power-Down Mode 2, 3 Power-Up Time2, 4 Reset Time2, 5 SERIAL INTERFACE 6, 7 SCL Frequency SCL High Pulse Width, tHIGH SCL Low Pulse Width, tLOW SCL, SDA Rise Time, tR SCL, SDA Fall Time, tF Hold Time (Start Condition), tHD;STA Setup Time (Start Condition), tSU;STA Data Setup Time, tSU;DAT Setup Time (Stop Condition), tSU;STO Data Hold Time (Master), tHD;DAT Bus-Free Time (Between Stop and Start Conditions), tBUF
1 2 3
Min
Typ
Max 20
Unit ms ms ms ms kHz s s s s s s s s ns s
Test Conditions/Comments Both channels, 10 ms per channel.
0.3 2 2 0 0.6 1.3 400
See Figure 2.
0.3 0.3 0.6 0.6 0.1 0.6 10 1.3
After this period, the first clock is generated. Relevant for repeated start condition.
Conversion time is 304 internal clock cycles for both channels (nominal clock 16 kHz); the internal clock frequency is equal to the specified excitation frequency. Specification is not production tested but is supported by characterization data at initial product release. Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion. 4 Power-up time is the maximum delay between the VDD crossing the minimum level (1.8 V) and either the start of conversion or when ready to receive a serial interface command. 5 Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial interface command. 6 Sample tested during initial release to ensure compliance. 7 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Output load = 10 pF.
tLOW
SCL
tR
tF
tHD;STA
tHD;STA
SDA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
tSU;STO
tBUF
P S
S
P
Figure 2. Serial Interface Timing Diagram
Rev. 0 | Page 5 of 28
07726-002
AD7156 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter Positive Supply Voltage VDD to GND Voltage on Any Input or Output to GND ESD Rating ESD Association Human Body Model, S5.1 Field-Inducted Charged Device Model Operating Temperature Range Storage Temperature Range Maximum Junction Temperature LFCSP Package JA, Thermal Impedance to Air JC, Thermal Impedance to Case Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature Rating -0.3 V to +3.9 V -0.3 V to VDD + 0.3 V 4 kV 500 V -40C to +85C -65C to +150C 150C 49C/W 3C/W 260(0/-5)C 10 sec to 40 sec
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 28
AD7156 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND 1 VDD 2 CIN2 3 CIN1 4 EXC2 5
10 SDA
AD7156
TOP VIEW (Not to Scale)
9 8 7 6
SCL OUT2 OUT1 EXC1
07726-003
NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO GND OR IT MUST BE ISOLATED (FLOATING).
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 Mnemonic GND VDD CIN2 Description Ground Pin. Power Supply Voltage. This pin should be decoupled to GND using a low impedance capacitor, such as a
0.1 F X7R multilayer ceramic capacitor.
CDC Capacitive Input Channel 2. The measured capacitance (sensor) is connected between the EXC2 pin and the CIN2 pin. If not used, this pin can be left open circuit or be connected to GND. When a conversion is performed on Channel 2, the CIN2 pin is internally connected to a high impedance input of the - modulator. When a conversion is performed on the other channel or in idle mode or power-down mode,
the CIN2 pin is internally disconnected and left floating by the part.
4 CIN1 CDC Capacitive Input Channel 1. The measured capacitance (sensor) is connected between the EXC1 pin and the CIN1 pin. If not used, this pin can be left open circuit or be connected to GND. When a conversion is performed on Channel 1, the CIN1 pin is internally connected to a high impedance input of the - modulator. When a conversion is performed on the other channel or in idle mode or power-down mode,
the CIN1 pin is internally disconnected and left floating by the part.
5 EXC2 CDC Excitation Output Channel 2. The measured capacitance is connected between the EXC2 pin and the CIN2 pin. If not used, this pin should be left as an open circuit. When a conversion is performed on Channel 2, the EXC2 pin is internally connected to the output of the excitation signal driver. When a conversion is performed on the other channel or in idle mode or power-down mode, the EXC2 pin is internally connected
to GND.
6 EXC1 CDC Excitation Output Channel 1. The measured capacitance is connected between the EXC1 pin and the CIN1 pin. If not used, this pin should be left as an open circuit. When a conversion is performed on Channel 1, the EXC1 pin is internally connected to the output of the excitation signal driver. When a conversion is performed on the other channel or in idle mode or power-down mode, the EXC1 pin is internally connected
to GND.
7 8 9 10 OUT1 OUT2 SCL SDA Logic Output Channel 1. A high level on this output indicates proximity detected on CIN1. Logic Output Channel 2. A high level on this output indicates proximity detected on CIN2. Serial Interface Clock Input. This pin connects to the master clock line and requires a pull-up resistor if not provided elsewhere in the system. Serial Interface Bidirectional Data. This pin connects to the master data line and requires a pull-up resistor if not provided elsewhere in the system.
Rev. 0 | Page 7 of 28
AD7156 TYPICAL PERFORMANCE CHARACTERISTICS
2.0 1.8 1.6
OFFSET ERROR (pF) OFFSET ERROR (fF)
1
0 1.8V -1
3.3V
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 300 CAPACITANCE CIN TO GROUND (pF) 3.3V
07726-004
1.8V
-2
-3
07726-007
-4 0 500 1000 1500 CAPACITANCE EXC TO GROUND (pF)
2000
Figure 4. Capacitance Input Offset Error vs. Capacitance CIN to GND, VDD = 1.8 V and 3.3 V, EXC Pin Open Circuit
5
Figure 7. Capacitance Input Offset Error vs. Capacitance EXC to GND, VDD = 1.8 V and 3.3 V, CIN Pin Open Circuit
1
0
GAIN ERROR (%FSR) GAIN ERROR (%FSR)
0 3.3V 1.8V -1
3.3V
-5
-10 1.8V -15
-2
-20
07726-005
-3
07726-008
-25 0 50 100 150 200 250 300 CAPACITANCE CIN TO GROUND (pF)
-4 0 500 1000 1500 CAPACITANCE EXC TO GROUND (pF)
2000
Figure 5. Capacitance Input Gain Error vs. Capacitance CIN to GND, VDD = 1.8 V and 3.3 V, CIN to EXC = 3 pF
5
Figure 8. Capacitance Input Gain Error vs. Capacitance EXC to GND, VDD = 1.8 V and 3.3 V, CIN to EXC = 3 pF
1
0
GAIN ERROR (%FSR) GAIN ERROR (%FSR)
0 3.3V
3.3V
-5
-1 1.8V -2
-10 1.8V -15
-20
07726-006
-3
07726-009
-25 0 50 100 150 200 250 300 CAPACITANCE CIN TO GROUND (pF)
-4 0 500 1000 1500 CAPACITANCE EXC TO GROUND (pF)
2000
Figure 6. Capacitance Input Gain Error vs. Capacitance CIN to GND, VDD = 1.8 V and 3.3 V, CIN to EXC = 9 pF
Figure 9. Capacitance Input Gain Error vs. Capacitance EXC to GND, VDD = 1.8 V and 3.3 V, CIN to EXC = 9 pF
Rev. 0 | Page 8 of 28
AD7156
2 0.2
0
GAIN ERROR (%FSR)
3.3V
GAIN ERROR (%FSR)
0 3.3V 1.8V -0.2 1.8V
-2
-4
-0.4
-6
-0.6
-8
07726-010
-0.8
07726-013
-10 1 10 100 1k RESISTANCE CIN TO GND (M)
-1.0 0.1
1
10
100
1k
RESISTANCE EXC TO GROUND (M)
Figure 10. Capacitance Input Gain Error vs. Resistance CIN to GND, VDD = 1.8 V and 3.3 V, CIN to EXC = 3 pF
2
Figure 13. Capacitance Input Gain Error vs. Resistance EXC to GND, VDD = 1.8 V and 3.3 V, CIN to EXC = 9 pF
1 0
0
GAIN ERROR (%FSR)
3.3V -1
GAIN ERROR (%FSR)
3.3V 1.8V
-2
-2 -3 -4 -5 1.8V
-4
-6
-8
07726-011
-10 1 10 100 1k RESISTANCE CIN TO GND (M)
-7 0 20 40 60 80 100 SERIAL RESISTANCE (k)
Figure 11. Capacitance Input Gain Error vs. Resistance CIN to GND, VDD = 1.8 V and 3.3 V, CIN to EXC = 9 pF
0.2 1.8V 3.3V -0.2
Figure 14. Capacitance Input Gain Error vs. Serial Resistance, VDD = 1.8 V and 3.3 V, CIN to EXC = 3 pF
10 1.8V
0
GAIN ERROR (%FSR)
0
GAIN ERROR (%FSR)
-10 3.3V -20
-0.4
-0.6
-30
-0.8
07726-012
-40
07726-015
-1.0 0.1
-50 1 10 100 1k PARELLEL RESISTANCE (M)
1
10
100
1k
RESISTANCE EXC TO GROUND (M)
Figure 12. Capacitance Input Gain Error vs. Resistance EXC to GND, VDD = 1.8 V and 3.3 V, CIN to EXC = 3 pF
Figure 15. Capacitance Input Gain Error vs. Parallel Resistance, VDD = 1.8 V and 3.3 V, CIN to EXC = 3 pF
Rev. 0 | Page 9 of 28
07726-014
-6
AD7156
5 4 3 10
OFFSET ERROR (fF)
20
2 1 0 -1 -2
3.3V 1.8V
DNL (fF)
07726-016
0
-10 -3 -4 -5 -50 -25 0 25 50 75 100
07726-019
-20 0 5 10 15 CAPDAC CODE 20 25 30
TEMPERATURE (C)
Figure 16. Capacitance Input Offset Error vs. Temperature, VDD = 1.8 V and 3.3 V, CIN and EXC Pins Open Circuit
0.35 0.25 0.15 0.05 -0.05 -0.15 -0.25 -0.35 -50
IDD MAX (A)
Figure 19. CAPDAC Differential Nonlinearity (DNL), VDD = 1.8 V
80 3.6V 70 2.7V 2V
GAIN ERROR (%FSR)
60
1.8V 50
07726-017
0
50
100
40 -50
-25
0
25
50
75
TEMPERATURE (C)
TEMPERATURE (C)
Figure 17. Capacitance Input Gain Error vs. Temperature, VDD = 2.7 V, CIN to EXC = 4 pF
16.50 16.25 2V 16.00 FREQUENCY (kHz) 3.6V 1.8V 15.50 15.25 15.00
07726-018
Figure 20. Current vs. Temperature, VDD = 1.8 V, 2 V, 2.7 V, and 3.6 V
4.0 3.5 3.0
IDD MAX (A)
2.7V
15.75
2.5 2.0 1.5 1.0 0.5 0 -50 3.6V 2.7V 2V -25 0 25 50 75 1.8V
14.50 -50
-25
0
25
50
75
100
TEMPERATURE (C)
TEMPERATURE (C)
Figure 18. EXC Frequency Error vs. Temperature, VDD = 1.8 V, 2 V, 2.7 V, and 3.6 V
Figure 21. Power-Down Current vs. Temperature, VDD = 1.8 V, 2 V, 2.7 V, and 3.6 V
Rev. 0 | Page 10 of 28
07726-021
14.75
07726-020
AD7156 THEORY OF OPERATION
3.3V VDD
AD7156
CIN1 CX1 EXC1 MUX CIN2 CX2 EXC2
CLOCK GENERATOR
POWER-DOWN TIMER SCL
- CDC
DIGITAL FILTER
SERIAL INTERFACE
SDA
PROGRAMMING INTERFACE
CAPDAC
THRESHOLD
OUT1 DIGITAL OUTPUTS
EXCITATION
THRESHOLD
OUT2
GND
Figure 22. AD7156 Block Diagram
The AD7156 core is a high performance capacitance-to-digital converter (CDC) that allows the part to be interfaced directly to a capacitive sensor. The comparators compare the CDC results with thresholds, either fixed or dynamically adjusted by the on-chip adaptive threshold algorithm engine. Thus, the outputs indicate a defined change in the input sensor capacitance. The AD7156 also integrates an excitation source, CAPDAC for the capacitive inputs, an input multiplexer, a complete clock generator, a power-down timer, a power supply monitor, control logic, and an I2C(R)-compatible serial interface for configuring the part and accessing the internal CDC data and status, if required in the system (see Figure 22).
CAPACITANCE-TO-DIGITAL CONVERTER (CDC) CLOCK GENERATOR 0x0000 TO 0xFFF0 DATA CIN CX 0pF TO 4pF EXC EXCITATION
07726-031
- MODULATOR
DIGITAL FILTER
Figure 23. CDC Simplified Block Diagram
CAPDAC
The AD7156 CDC core maximum full-scale input range is 0 pF to 4 pF. However, the part can accept a higher input capacitance, caused, for example, by a nonchanging offset capacitance of up to 10 pF. This offset capacitance can be compensated for by using the programmable on-chip CAPDAC.
CAPDAC 10pF CIN CX 10pF TO 14pF
07726-032
CAPACITANCE-TO-DIGITAL CONVERTER
Figure 23 shows the CDC simplified functional diagram. The converter consists of a second-order - charge balancing modulator and a third-order digital filter. The measured capacitance CX is connected between an excitation source and the - modulator input. The excitation signal is applied on the CX capacitor during the conversion, and the modulator continuously samples the charge going through the CX. The digital filter processes the modulator output, which is a stream of 0s and 1s containing the information in 0 and 1 density. The data is processed by the adaptive threshold engine and output comparators; the data can also be read through the serial interface. The AD7156 is designed for floating capacitive sensors. Therefore, both CX plates have to be isolated from ground or any other fixed potential node in the system. The AD7156 features slew rate limiting on the excitation voltage output, which decreases the energy of higher harmonics on the excitation signal and dramatically improves the system electromagnetic compatibility (EMC).
0x0000 TO 0xFFF0 DATA 0pF TO 4pF
EXC
Figure 24. Using a CAPDAC
The CAPDAC can be understood as a negative capacitance connected internally to a CIN pin. The CAPDAC has a 6-bit resolution and a monotonic transfer function. Figure 24 shows how to use the CAPDAC to shift the CDC 0 pF to 4 pF input range to measure capacitance between 10 pF and 14 pF.
Rev. 0 | Page 11 of 28
07726-030
AD7156
COMPARATOR AND THRESHOLD MODES
The AD7156 comparators and their thresholds can be programmed to operate in two modes: fixed and adaptive threshold modes. In an adaptive mode, the threshold is dynamically adjusted and the comparator output indicates fast changes and ignores slow changes in the input (sensor) capacitance. Alternatively, the threshold can be programmed as a constant (fixed) value, and the output then indicates any change in the input capacitance that crosses the defined fixed threshold. The AD7156 logic output (active high) indicates either a positive or a negative change in the input capacitance, in both adaptive and fixed threshold modes (see Figure 25 and Figure 26).
POSITIVE CHANGE POSITIVE THRESHOLD INPUT CAPACITANCE OUTPUT ACTIVE
INPUT CAPACITANCE
07726-033
INPUT OUTSIDE THRESHOLD WINDOW POSITIVE THRESHOLD INPUT CAPACITANCE NEGATIVE THRESHOLD OUTPUT ACTIVE
07726-036
07726-039
07726-037
OUTPUT TIME
Figure 28. Out-Window (Adaptive) Threshold Mode
ADAPTIVE THRESHOLD
In an adaptive mode, the thresholds are dynamically adjusted, ensuring indication of fast changes (for example, an object moving close to a capacitive proximity sensor) and eliminating slow changes in the input (sensor) capacitance, usually caused by environment changes such as humidity or temperature or changes in the sensor dielectric material over time (see Figure 29).
FAST CHANGE SLOW CHANGE
OUTPUT TIME
THRESHOLD
OUTPUT ACTIVE OUTPUT TIME
Figure 25. Positive Threshold Mode Indicates Positive Change in Input Capacitance
NEGATIVE CHANGE INPUT CAPACITANCE NEGATIVE THRESHOLD OUTPUT ACTIVE
Figure 29. Adaptive Threshold Indicates Fast Changes and Eliminates Slow Changes in Input Capacitance
SENSITIVITY
In adaptive threshold mode, the output comparator threshold is set as a defined distance (sensitivity) above the data average, below the data average, or both, depending on the selected threshold mode of operation (see Figure 30). The sensitivity value is programmable in the range of 0 LSB to 255 LSB of the 12-bit CDC converter (see the Register Descriptions section).
DATA POSITIVE THRESHOLD SENSITIVITY DATA AVERAGE SENSITIVITY NEGATIVE THRESHOLD OUTPUT ACTIVE
TIME
Figure 26. Negative Threshold Mode Indicates Negative Change in Input Capacitance
Additionally, for the adaptive mode only, the comparators can work as window comparators, indicating input either inside or outside a selected sensitivity band (see Figure 27 and Figure 28).
POSITIVE THRESHOLD INPUT CAPACITANCE NEGATIVE THRESHOLD OUTPUT ACTIVE
07726-035
INPUT INSIDE THRESHOLD WINDOW
07726-034
OUTPUT
TIME
Figure 30. Threshold Sensitivity
OUTPUT TIME
Figure 27. In-Window (Adaptive) Threshold Mode
Rev. 0 | Page 12 of 28
AD7156
DATA AVERAGE
The adaptive threshold algorithm is based on an average calculated from the previous CDC output data, using the following equation:
Average(N ) = Average(N - 1) + Data(N ) - Average(N - 1) 2ThrSettling
+1
TIMEOUT
In the case of a large, long change in the capacitive input, when the data average adapting to a new condition takes too long, a timeout can be set. The timeout becomes active (counting) when the CDC data goes outside the band of data average sensitivity. When the timeout elapses (a defined number of CDC conversions is counted), the data average (and thus the thresholds), is forced to follow the new CDC data value immediately (see Figure 33). The timeout can be set independently for approaching (for change in data toward the threshold) and for receding (for change in data away from the threshold). See Figure 34, Figure 35, and the Register Descriptions section for further information.
DATA AVERAGE + SENSITIVITY DATA AVERAGE DATA AVERAGE - SENSITIVITY LARGE CHANGE IN DATA
where: Average(N) is the new average value. Average(N - 1) is the average value from the previous cycle. Data(N) is the latest complete CDC conversion result. ThrSettling is a parameter, programmable in the setup registers. A more specific case of the input capacitance waveform is a step change. The response of the average to an input capacitance step change (more exactly, response to a step change in the CDC output data) is an exponential settling curve, which can be characterized by the following equation:
Average(N ) = Average(0) + Change(1 - e N /TimeConst ) where: Average(N) is the value of average N complete CDC conversion cycles after a step change on the input. Average(0) is the value before the step change. TimeConst = 2(ThrSettling + 1) ThrSettling is a parameter, programmable in the setup registers. See Figure 31 and the Register Descriptions section for further information.
INPUT CAPACITANCE (CDC DATA) CHANGE
TIMEOUT
TIME
Figure 33. Threshold Timeout After a Large Change in CDC Data
TIMEOUT APPROACHING INPUT CAPACITANCE THRESHOLD DATA AVERAGE
07726-038
DATA AVERAGE RESPONSE TIME
OUTPUT ACTIVE OUTPUT
07726-042
Figure 31. Data Average Response to Data Step Change
TIME
HYSTERESIS
In adaptive threshold mode, the comparator features hysteresis. The hysteresis is fixed to 1/4 of the threshold sensitivity and can be programmed on or off. The comparator does not have hysteresis in the fixed threshold mode.
DATA POSITIVE THRESHOLD
Figure 34. Approaching Timeout in Negative Threshold Mode Shortens False Output Trigger
TIMEOUT RECEDING
LARGE CHANGE
HYSTERSIS
INPUT CAPACITANCE THRESHOLD
DATA AVERAGE OUTPUT ACTIVE
07726-040
OUTPUT ACTIVE OUTPUT TIME
07726-041
OUTPUT
TIME
Figure 32. Threshold Hysteresis
Figure 35. Positive Timeout in Negative Threshold Mode Shortens Period of Missing Output Trigger
Rev. 0 | Page 13 of 28
07726-043
AD7156
AUTO-DAC ADJUSTMENT
In adaptive threshold mode, the part can dynamically adjust the CAPDAC to keep the CDC in an optimal operating capacitive range. When the auto-DAC function is enabled, the CAPDAC value is automatically incremented when the data average exceeds 3/4 of the CDC full range (average > 0xA800), and the CAPDAC value is decremented when the data average goes below 1/4 of the CDC full range (average < 0x5800). The auto-DAC increment or decrement step depends on the selected CDC capacitive input range (see the Setup Registers section). When the CAPDAC value reaches 0, the 1/4 threshold for further decrementing is ignored. Similarly, when the CAPDAC value reaches its full range, the 3/4 threshold is ignored. The CDC and the rest of the algorithm are continuously working, and they are functional down to a capacitance input of 0 pF or as high as the capacitance input of (CAPDAC full range + CDC full range), respectively.
POWER-DOWN TIMER
In power sensitive applications, the AD7156 can be set to automatically enter power-down mode after a programmed period of time in which the outputs have not been activated. The AD7156 can then be returned to a normal operational mode either via the serial interface or by the power supply off/on sequence.
Rev. 0 | Page 14 of 28
AD7156 REGISTER DESCRIPTIONS
Table 5. Register Summary 1
Register Status Ch 1 Data High Ch 1 Data Low Ch 2 Data High Ch 2 Data Low Ch 1 Average High Ch 1 Average Low Ch 2 Average High Ch 2 Average Low Ch 1 Sensitivity/ Ch 1 Threshold High Ch 1 Timeout/ Ch 1 Threshold Low Ch 1 Setup Ch 2 Sensitivity/ Ch 2 Threshold High Ch 2 Timeout/ Ch 2 Threshold Low Ch 2 Setup Configuration Power-Down Timer Ch 1 CAPDAC Ch 2 CAPDAC Serial Number 3 Serial Number 2 Serial Number 1 Serial Number 0 Chip ID
1
Addr Pointer Dec Hex 0 0x00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
R/W R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R
Bit 7 PwrDown
Bit 6 DacStep2
Bit 5 OUT2
Bit 4 DacStep1
Bit 3 OUT1
Bit 2 C1/C2
Bit 1 RDY2
Bit 0 RDY1
(0)
(1)
(0)
(1)
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
(0)
(0)
(1)
(1)
Ch 1 sensitivity (in adaptive threshold mode)/Ch 1 threshold high byte (in fixed threshold mode) 0x08 Ch 1 timeout (in adaptive threshold mode)/CH 1threshold low byte (in fixed threshold mode) 0x86 RngH1 RngL1 Hyst1 ThrSettling1 (4-bit value) (0) (0) (0) (0) (0x0B) Ch 2 sensitivity (in adaptive threshold mode)/Ch 2 threshold high byte (in fixed threshold mode) 0x08 Ch 2 timeout (in adaptive threshold mode)/Ch 2 threshold low byte (in fixed threshold mode) 0x86 RngH2 (0) ThrFixed (0) RngL2 (0) ThrMD1 (0) (0) ThrMD0 (0) Hyst2 ThrSettling2 (4-bit value) MD0 (1) (0) (0x0B) EnCh1 EnCh2 MD2 MD1 (1) (1) (0) (0) Power-down timeout (6-bit value) (0x00) DacValue1 (6-bit value) (0x00) DacValue2 (6-bit value) (0x00)
(0) (1) DacEn1 DacAuto1 (1) (1) DacEn2 DacAuto2 (1) (1) Serial number--Byte 3 (MSB) Serial number--Byte 2 Serial number--Byte 1 Serial number--Byte 0 (LSB) Chip identification code
The default values are given in parentheses.
Rev. 0 | Page 15 of 28
AD7156
STATUS REGISTER
Address Pointer 0x00 8 Bits, Read Only Default Value 0x53 Before Conversion, 0x54 After Conversion
The status register indicates the status of the part. The register can be read via the 2-wire serial interface to query the status of the outputs, check the CDC finished conversion, and check whether the CAPDAC has been changed by the auto-DAC function.
Table 6. Status Register Bit Map 1
Bit 7 PwrDown (0)
1
Bit 6 DacStep2 (1)
Bit 5 OUT2 (0)
Bit 4 DacStep1 (1)
Bit 3 OUT1 (0)
Bit 2 C1/C2 (0)
Bit 1 RDY2 (1)
Bit 0 RDY1 (1)
The default values are given in parentheses.
Table 7. Status Register Bit Descriptions
Bit 7 6 5 4 3 2 1 0 Mnemonic PwrDown DacStep2 OUT2 DacStep1 OUT1 C1/C2 RDY2 RDY1 Description PwrDown = 1 indicates that the part is in a power-down. DacStep2 = 0 indicates that the Channel 2 CAPDAC value was changed after the last CDC conversion as part of the auto-DAC function. The bit value is updated after each finished CDC conversion on this channel. OUT2 = 1 indicates that the Channel 2 data (CIN2 capacitance) crossed the threshold, according to the selected comparator mode of operation. The bit value is updated after each finished CDC conversion on this channel. DacStep1 = 0 indicates that the Channel 1 CAPDAC value was changed during the last conversion as part of the auto-DAC function. The bit value is updated after each finished CDC conversion on this channel. OUT1 = 1 indicates that the Channel 1 data (CIN1 capacitance) crossed the threshold, according to the selected comparator mode of operation. The bit value is updated after each finished CDC conversion on this channel. C1/C2 = 0 indicates that the last finished CDC conversion was on Channel 1. C1/C2 = 1 indicates that the last finished CDC conversion was on Channel 2. RDY2 = 0 indicates a finished CDC conversion on Channel 2. The bit is reset back to 1 when the Channel 2 data register is read via the serial interface or after a part reset or power-up. RDY1 = 0 indicates a finished CDC conversion on Channel 1. The bit is reset back to 1 when the Channel 1 data register is read via serial interface or after a part reset or power-up.
Rev. 0 | Page 16 of 28
AD7156
DATA REGISTERS
Ch 1 Address Pointer 0x01, Address Pointer 0x02 Ch 2 Address Pointer 0x03, Address Pointer 0x04 16 Bits, Read Only Default Value 0x0000
Data from the last complete capacitance-to-digital conversion reflects the capacitance on the input. Only the 12 MSBs of the data registers are used for the CDC result. The 4 LSBs are always 0, as shown in Figure 36. The data register is updated after a finished conversion on the capacitive channel, with one exception: when the serial interface read operation from the data register is in progress, the data register is not updated and the new capacitance conversion result is lost. The stop condition on the serial interface is considered to be the end of the read operation. Therefore, to prevent incorrect data reading through the serial interface, the two bytes of a data register should be read sequentially using the register address pointer autoincrement feature of the serial interface. The nominal AD7156 CDC transfer function (an ideal transfer function excluding offset and/or gain error) maps the input capacitance between zero scale and full scale to output data codes between 0x3000 and 0xD000 only (see Table 8). For an ideal part, linear, with no offset error and no gain error, the input capacitance can be calculated from the output data using the following equation:
C (pF) =
Data - 12,288 40,960
x Input _ Range (pF)
where Input_Range = 4 pF, 2 pF, 1 pF, or 0.5 pF. The following is the same equation written with hexadecimal numbers:
C (pF) = Data - 0 x3000 0 xA000 x Input _ Range (pF)
With offset error and gain error included, the equation is:
C (pF) =
x Input _ Range (pF) x 40,960 Gain _ Error(%) + Offset _ Error (pF) 1 + 100%
Data - 0 x3000
Data - 12,288
Or the same equation with hexadecimal numbers:
C (pF) = x Input _ Range (pF) x 0 xA000 Gain _ Error(%) 1 + + Offset _ Error (pF) 100%
MSB
DATA HIGH
DATA LOW
LSB
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 12-BIT CDC RESULT 0
07726-044
Figure 36. CDC Data Register
Table 8. AD7156 Capacitance-to-Data Mapping 1
Data 0x0000 0x3000 0x5800 0x8000 0xA800 0xD000 0xFFF0
1
Input Capacitance Under range (below 0 pF) Zero scale (0 pF) Quarter scale (+0.5 pF)--auto-DAC step down Midscale (+1 pF) Three-quarter scale (+1.5 pF)--auto-DAC step up Full scale (+2 pF) Over range (above +2 pF)
An ideal part with no offset and gain error, values shown in picofarad for 2 pF capacitance input range.
Rev. 0 | Page 17 of 28
AD7156
AVERAGE REGISTERS
Ch 1 Address Pointer 0x05, Address Pointer 0x06 Ch 2 Address Pointer 0x07, Address Pointer 0x08 16 Bits, Read Only Default Value 0x0000
These registers show the average calculated from the previous CDC data. The 12-bit CDC result corresponds to the 12 MSBs of the average register. The settling time of the average can be set by programming the ThrSettling bits in the setup registers. The average register is overwritten directly with the CDC output data, that is, the history is erased if the timeout is enabled and elapses. For an ideal part with no gain error, the sensitivity can be calculated using the following equation:
Sensitivity (pF) = Sens _ Reg x Input _ Range (pF) 2560
Or the same equation with hexadecimal numbers
Sensitivity (pF) =
Sens _ Reg x Input _ Range (pF) 0 xA00
With gain error included, the sensitivity can be calculated using the following equation:
FIXED THRESHOLD REGISTERS
Ch 1 Address Pointer 0x09, Address Pointer 0x0A Ch 2 Address Pointer 0x0C, Address Pointer 0x0D 16 Bits, Read/Write, Factory Preset 0x0886
A constant threshold for the output comparator in the fixed threshold mode can be set using these registers. The 12-bit CDC result corresponds to the 12 MSBs of the threshold register. The fixed threshold registers share the address pointer and location on chip with the sensitivity and timeout registers. The fixed threshold registers are not accessible in the adaptive threshold mode.
Sense _ Reg x Input _ Range (pF) x 2560 Gain _ Error (%) 1 + 100% Sensitivity (pF) = Or the same equation with hexadecimal numbers
Sense _ Reg x Input _ Range (pF) x 0 xA00 Gain _ Error (%) 1 + 100% Sensitivity (pF) =
TIMEOUT REGISTERS
Ch 1 Address Pointer 0x0A Ch 2 Address Pointer 0x0D 8 Bits, Read/Write, Factory Preset 0x86
Table 9. Timeout Register Bit Map
Bit [7:4] [3:0] Mnemonic TimeOutApr TimeOutRec Default 0x08 0x06
SENSITIVITY REGISTERS
Ch 1 Address Pointer 0x09 Ch 2 Address Pointer 0x0C 8 Bits, Read/Write, Factory Preset 0x08
Sensitivity registers set the distance of the positive threshold above the data average, and the distance of the negative threshold below the data average, in the adaptive threshold mode.
DATA POSITIVE THRESHOLD SENSITIVITY DATA AVERAGE SENSITIVITY NEGATIVE THRESHOLD OUTPUT ACTIVE
07726-045
These registers set timeouts for the adaptive threshold mode. The approaching timeout starts when the CDC data crosses the data average sensitivity band toward the threshold, according to the selected positive, negative, or window threshold mode. The approaching timeout elapses after the number of conversion cycles equals 2TimeOutApr, where TimeOutApr is the value of the four most significant bits of the timeout register. The receding timeout starts when the CDC data crosses the data average sensitivity band away from the threshold, according to the selected positive or negative threshold mode. The receding timeout is not used in the window threshold mode. The receding timeout elapses after the number of conversion cycles equals 2TimeOutRec, where TimeOutRec is the value of the four least significant bits of the timeout register. When either the approaching or receding timeout elapses (that is, after the defined number of CDC conversions is counted), the data average (and thus the thresholds) is forced to follow the new CDC data value immediately. When the timeout register equals 0, timeouts are disabled.
TIME
Figure 37. Threshold Sensitivity
The sensitivity is an 8-bit value and is mapped to the lower eight bits of the 12-bit CDC data, that is, it corresponds to the 16-bit data register as shown in Figure 38.
SENSITIVITY BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DATA HIGH BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DATA LOW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
07726-046
12-BIT CDC RESULT
Figure 38. Relation Between Sensitivity Register and CDC Data Register
Rev. 0 | Page 18 of 28
AD7156
SETUP REGISTERS
Ch 1 Address Pointer 0x0B Ch 2 Address Pointer 0x0E 8 Bits, Read/Write, Factory Preset 0x0B
Table 10. Setup Registers Bit Map 1
Bit 7 RngH (0)
1
Bit 6 RngL (0)
Bit 5 (0)
Bit 4 Hyst (0)
Bit 3
Bit 2 Bit 1 ThrSettling (4-Bit Value) (0x0B)
Bit 0
The default values are given in parentheses.
Table 11. Setup Registers Bit Descriptions
Bit 7 6 Mnemonic RngH RngL Description Range bits set the CDC input range and determine the step for the auto-DAC function. RngH RngL Capacitive Input Range (pF) Auto-DAC Step (CAPDAC LSB) 0 0 1 1 5 4 [3:0] Hyst ThrSettling 0 1 0 1 2 0.5 1 4 4 1 2 8
This bit should be 0 for the specified operation. Hyst = 1 disables hysteresis in adaptive threshold mode. This bit has no effect in fixed threshold mode; hysteresis is always disabled in the fixed threshold mode. Determines dynamic behavior of the data average and thus the settling time of the adaptive thresholds. Data average is calculated from the previous CDC output data, using equation:
Average( N ) = Average( N - 1) +
Data( N ) - Average(N - 1) 2 ThrSettling + 1
where: Average(N) is the new average value. Average(N - 1) is the average value from the previous cycle. Data(N) is the latest complete CDC conversion result. ThrSettling is the programmable parameter. The response of the average to an input capacitance step change (that is, response to the change in the CDC output data) is an exponential settling curve characterized by the following equation:
Average(N ) = Average( 0 ) + Change(1 - e N / TimeConst )
where: Average(N) is the value of average N complete CDC conversion cycles after a step change on the input. Average(0) is the value before the step change. TimeConst can be selected in the range between 2 and 65,536 conversion cycle multiples, in steps of power of 2, by programming the ThrSettling bits. TimeConst = 2(ThrSettling + 1)
INPUT CAPACITANCE (CDC DATA) CHANGE
TIME
Figure 39. Data Average Response to Data Step Change
Rev. 0 | Page 19 of 28
07726-049
DATA AVERAGE RESPONSE
AD7156
CONFIGURATION REGISTER
Address Pointer 0x0F 8 Bits, Read/Write, Factory Preset 0x19
Table 12. Configuration Register Bit Map 1
Bit 7 ThrFixed (0)
1
Bit 6 ThrMD1 (0)
Bit 5 ThrMD0 (0)
Bit 4 EnCh1 (1)
Bit 3 EnCh2 (1)
Bit 2 MD2 (0)
Bit 1 MD1 (0)
Bit 0 MD0 (1)
The default values are given in parentheses.
Table 13.Configuration Register Bit Descriptions
Bit 7 Mnemonic ThrFixed Description ThrFixed = 1 sets the fixed threshold mode; the outputs reflect the comparison of data and a fixed (constant) value of the threshold registers. ThrFixed = 0 sets the adaptive threshold mode; the outputs reflect the comparison of data to the adaptive thresholds. The adaptive threshold is set dynamically, based on the history of the previous data. These bits set the output comparators mode Output Active When ThrMD1 ThrMD0 Threshold Mode Adaptive Threshold Mode Fixed Threshold Mode 0 0 Negative Data < average - sensitivity Data < threshold 0 1 Positive Data > average + sensitivity Data > threshold 1 0 In-window Data > average - sensitivity and Data < average + sensitivity 1 1 Out-window Data < average - sensitivity or Data > average + sensitivity Enables conversion on Channel 1 Enables conversion on Channel 2 Converter mode of operation setup MD2 MD1 MD0 Mode Description 0 0 0 Idle The part is fully powered up, but performing no conversion. 0 0 1 Continuous The part is repeatedly performing conversions on the Conversion enabled channel(s); if two channels are enabled, the part is sequentially switching between them. 0 1 0 Single conversion The part performs a single conversion on the enabled channel; if two channels are enabled, the part performs two conversions, one on each channel. After finishing the conversion(s), the part goes to the idle mode. 0 1 1 Power-down The part powers down the on-chip circuits, except the digital interface. 1 X X Reserved Do not use these modes.
6 5
ThrMD1 ThrMD0
4 3 2 1 0
EnCh1 EnCh2 MD2 MD1 MD0
Rev. 0 | Page 20 of 28
AD7156
POWER-DOWN TIMER REGISTER
Address Pointer 0x10 8 Bits, Read/Write, Factory Preset 0x40
Table 14. Power-Down Timer Register Bit Map 1
Bit 7 (0)
1
Bit 6 (1)
Bit 5
Bit 4
Bit 3 Bit 2 Power-down timeout (6-bit value) (0x00)
Bit 1
Bit 0
The default values are given in parentheses.
Table 15.Power-Down Timer Register Bit Descriptions
Bit 7 6 [5:0] Mnemonic Description This bit must be 0 for proper operation. This bit must be 1 for proper operation. This bit defines the period duration of the power-down timeout. If the comparator outputs have not been activated during the programmed period, the part enters power-down mode automatically. The part can be then returned to a normal operational mode either via the serial interface or by the power supply off/on sequence. The period is programmable in steps of 4 hours. For example, setting the value to 0x06 sets the duration to 24 hours. The maximum value of 0x3F corresponds to approximately 10.5 days. The value of 0x00 disables the power-down timeout, and the part does not enter power-down mode automatically.
Power-down timeout
CAPDAC REGISTERS
Ch 1 Address Pointer 0x11 Ch 2 Address Pointer 0x12 8 Bits, Read/Write, Factory Preset 0xC0
Table 16. CAPDAC Registers Bit Map 1
Bit 7 DacEn (1)
1
Bit 6 DacAuto (1)
Bit 5
Bit 4
Bit 3 Bit 2 DacValue (6-bit value) (0x00)
Bit 1
Bit 0
The default values are given in parentheses.
Table 17. CAPDAC Registers Bit Descriptions
Bit 7 6 Mnemonic DacEn DacAuto Description DacEn = 1 enables capacitive the DAC. DacAuto = 1 enables the auto-DAC function in the adaptive threshold mode. When the auto-DAC function is enabled, the part dynamically adjusts the CAPDAC to keep the CDC in an optimal operating capacitive range. The CAPDAC value is automatically incremented when the data average exceeds 3/4 of the CDC full range, and the CAPDAC value is decremented when the data average goes below 1/4 of the CDC full range. The auto-DAC increment or decrement step depends on the selected CDC capacitive input range. This bit has no effect in fixed threshold mode; the auto-DAC function is always disabled in the fixed threshold mode. CAPDAC value, Code 0x00 0 pF, Code 0x3F CAPDAC full range.
[5:0]
DacValue
SERIAL NUMBER REGISTER
Address Pointer 0x13, Address Pointer 0x14, Address Pointer 0x15, Address Pointer 0x16 32 Bits, Read Only, Factory Preset 0xXXXX
This register holds a serial number, unique for each individual part.
CHIP ID REGISTER
Address Pointer 0x17 8 Bits, Read Only, Factory Preset 0xXX
This register holds the chip identification code, used in factory manufacturing and testing.
Rev. 0 | Page 21 of 28
AD7156 SERIAL INTERFACE
The AD7156 supports an I2C-compatible, 2-wire serial interface. The two wires on the serial bus (interface) are called SCL (clock) and SDA (data). These two wires carry all addressing, control, and data information one bit at a time over the bus to all connected peripheral devices. The SDA wire carries the data, while the SCL wire synchronizes the sender and receiver during the data transfer. The devices on the bus are classified as either master or slave devices. A device that initiates a data transfer message is called a master, whereas a device that responds to this message is called a slave. To control the AD7156 device on the bus, the following protocol must be utilized. First, the master initiates a data transfer by establishing a start condition, defined by a highto-low transition on SDA while SCL remains high. This indicates that the start byte follows. This 8-bit start byte is made up of a 7-bit address plus an R/W bit indicator. All peripherals connected to the bus respond to the start condition and shift in the next eight bits (7-bit address + R/W bit). The bits arrive MSB first. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as the acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. An exception to this is the general call address, which is described in the General Call section. In the idle condition, the device monitors the SDA and SCL lines waiting for the start condition and the correct address byte. The R/W bit determines the direction of the data transfer. A Logic 0 LSB in the start byte means that the master writes information to the addressed peripheral. In this case, the AD7156 becomes a slave receiver. A Logic 1 LSB in the start byte means that the master reads information from the addressed peripheral. In this case, the AD7156 becomes a slave transmitter. In all instances, the AD7156 acts as a standard slave device on the serial bus. The start byte address for the AD7156 is 0x90 for a write and 0x91 for a read. In continuous conversion mode, the address pointers' autoincrementer should be used for reading a conversion result. This means that the two data bytes should be read using one multibyte read transaction rather than two separate single byte transactions. The single byte data read transaction may result in the data bytes from two different results being mixed. The same applies for four data bytes if both capacitive channels are enabled. The user can also access any unique register (address) on a one-to-one basis without having to update all the registers. The address pointer register contents cannot be read. If an incorrect address pointer location is accessed or if the user allows the autoincrementer to exceed the required register address, the following applies:
*
*
In read mode, the AD7156 continues to output various internal register contents until the master device issues a no acknowledge, start, or stop condition. The address pointers' autoincrementer contents are reset to point to the status register at the 0x00 address when a stop condition is received at the end of a read operation. This allows the status register to be read (polled) continually without having to constantly write to the address pointer. In write mode, the data for the invalid address is not loaded into the AD7156 registers, but an acknowledge is issued by the AD7156.
WRITE OPERATION
When a write is selected, the byte following the start byte is always the register address pointer (subaddress) byte, which points to one of the internal registers on the AD7156. The address pointer byte is automatically loaded into the address pointer register and acknowledged by the AD7156. After the address pointer byte acknowledge, a stop condition, a repeated start condition, or another data byte can follow from the master. A stop condition is defined by a low-to-high transition on SDA while SCL remains high. If a stop condition is encountered by the AD7156, it returns to its idle condition and the address pointer is reset to 0x00. If a data byte is transmitted after the register address pointer byte, the AD7156 loads this byte into the register that is currently addressed by the address pointer register and sends an acknowledge, and the address pointer autoincrementer automatically increments the address pointer register to the next internal register address. Thus, subsequent transmitted data bytes are loaded into sequentially incremented addresses.
READ OPERATION
When a read is selected in the start byte, the register that is currently addressed by the address pointer is transmitted to the SDA line by the AD7156. This is then clocked out by the master device, and the AD7156 awaits an acknowledge from the master. If an acknowledge is received from the master, the address autoincrementer automatically increments the address pointer register and outputs the next addressed register content to the SDA line for transmission to the master. If no acknowledge is received, the AD7156 returns to the idle state and the address pointer is not incremented. The address pointers' autoincrementer allows block data to be written to or read from the starting address and subsequent incremental addresses.
Rev. 0 | Page 22 of 28
AD7156
If a repeated start condition is encountered after the address pointer byte, all peripherals connected to the bus respond exactly as outlined previously for a start condition; that is, a repeated start condition is treated the same as a start condition. When a master device issues a stop condition, it relinquishes control of the bus, allowing another master device to take control of the bus. Therefore, a master wanting to retain control of the bus issues successive start conditions known as repeated start conditions.
GENERAL CALL
When a master issues a slave address consisting of seven 0s with the eighth bit (R/W) set to 0, this is known as the general call address. The general call address is for addressing every device connected to the serial bus. The AD7156 acknowledges this address and reads in the following data byte. If the second byte is 0x06, the AD7156 is reset, completely uploading all default values. The AD7156 does not respond to the serial bus commands (do not acknowledge) during the default values upload for approximately 2 ms. The AD7156 does not acknowledge any other general call commands.
AD7156 RESET
To reset the AD7156 without having to reset the entire serial bus, an explicit reset command is provided. This uses a particular address pointer word as a command word to reset the part and upload all default settings. The AD7156 does not respond to the serial bus commands (do not acknowledge) during the default values upload for approximately 2 ms. The reset command address word is 0xBF.
SDA
1-7
1-7
1-7
START ADDR R/W ACK SUBADDRESS ACK
DATA
ACK
STOP
Figure 40. Bus Data Transfer
WRITE SEQUENCE
S
SLAVE ADDR
A(S)
SUB ADDR
A(S)
DATA
A(S) LSB = 1
DATA
A(S) P
LSB = 0 READ SEQUENCE S SLAVE ADDR S = START BIT P = STOP BIT A(S) SUB ADDR A(S) S
07726-050
SCL S
8
9
8
9
8
9
P
SLAVE ADDR
A(S)
DATA
A(M)
DATA
A(M) P
07726-051
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO ACKNOWLEDGE BY SLAVE A(M) = NO ACKNOWLEDGE BY MASTER
Figure 41. Write and Read Sequences
Rev. 0 | Page 23 of 28
AD7156 HARDWARE DESIGN CONSIDERATIONS
OVERVIEW
The AD7156 is an interface to capacitive sensors. On the input side, Sensor CX can be connected directly between the AD7156 EXC and CIN pins. The way it is connected and the electrical parameters of the sensor connection, such as parasitic resistance or capacitance, can affect the system performance. Therefore, any circuit with additional components in the capacitive front end, such as overvoltage protection, has to be carefully designed, considering the AD7156 specified limits and information provided in this section. On the output side, the AD7156 can work as a standalone device, using the power-up default register settings and flagging the result on the digital outputs. Alternatively, the AD7156 can be interfaced to a microcontroller via the 2-wire serial interface, offering flexibility by overwriting the AD7156 register values from the host with a user-specific setup.
RGND1 DATA
PARASITIC RESISTANCE TO GROUND
CIN
CDC
CX
RGND2
Figure 43. Parasitic Resistance to Ground
PARASITIC CAPACITANCE TO GROUND
The AD7156 CDC result is affected by a leakage current from CX to ground; therefore, CX should be isolated from the ground. The equivalent resistance between CX and ground should be maximized (see Figure 43). For more information, see Figure 10 to Figure 13.
PARASITIC PARALLEL RESISTANCE
CGND1 CIN DATA
CDC
CIN
CDC
DATA
CX
CX
CGND2
07726-052
RP
EXC
EXC
Figure 42. Parasitic Capacitance to Ground Figure 44. Parasitic Parallel Resistance
The CDC architecture used in the AD7156 measures the capacitance, CX, connected between the EXC pins and the CIN pins. In theory, any capacitance, CGND, to ground should not affect the CDC result (see Figure 42). The practical implementation of the circuitry in the chip implies certain limits, and the result is gradually affected by capacitance to ground (for information about the allowed capacitance to GND for CIN and information about excitation see Table 1 and Figure 4 to Figure 9).
The AD7156 CDC measures the charge transfer between the EXC and CIN pins. Any resistance connected in parallel to the measured capacitance, CX (see Figure 44), such as the parasitic resistance of the sensor, also transfers charge. Therefore, the parallel resistor is seen as an additional capacitance in the output data. The equivalent parallel capacitance (or error caused by the parallel resistance) can be approximately calculated as
CP = 1 R P x f EXC x 4
where: RP is the parallel resistance. fEXC is the excitation frequency. For additional information, see Figure 15.
Rev. 0 | Page 24 of 28
07726-054
07726-053
EXC
AD7156
PARASITIC SERIAL RESISTANCE INPUT EMC PROTECTION
39k CX 82k 68pF 10k CIN 22pF EXC
07726-057
RS1
CIN
CDC
DATA
CDC
47pF
CX
GND
Figure 47. AD7156 CIN EMC Protection
EXC
07726-055
RS2
Figure 45. Parasitic Serial Resistance
The AD7156 CDC result is affected by a resistance in series with the measured capacitance. The total serial resistance (RS1 + RS2 in Figure 45) should be in the order of hundreds of (see Figure 14).
Some applications may require an additional input filter for improving EMC. Any input filter must be carefully designed, considering the balance between the system capacitance performance and system electromagnetic immunity. Figure 47 shows one of the possible input circuit configurations for significantly improving the system immunity against high frequency noise while only slightly affecting the AD7156 performance in terms of additional gain and offset error.
INPUT OVERVOLTAGE PROTECTION
CDC RS1 CX RS2 EXC CIN
POWER SUPPLY DECOUPLING AND FILTERING
1k 0.1F 10F 1k SDA CDC SCL 1k VDD
07726-056
GND
GND
Figure 46. AD7156 CIN Overvoltage Protection
Figure 48. AD7156 VDD Decoupling and Filtering
The AD7156 capacitive input has an internal ESD protection. However, some applications may require an additional overvoltage protection, depending on the application-specific requirements. Any additional circuit in the capacitive front end must be carefully designed, especially with respect to the limits recommended for maximum capacitance to ground, maximum serial resistance, maximum leakage, and so on.
The AD7156 has good dc and low frequency power supply rejection but may be sensitive to higher frequency ripple and noise, specifically around the excitation frequency and its harmonics. Figure 48 shows a possible circuit configuration for improving the system immunity against ripple and noise coupled to the AD7156 via the power supply. If the serial interface is connected to the other circuits in the system, it is better to connect the pull-up resistors on the other side of the VDD filter than to connect to the AD7156. If the AD7156 is used in standalone mode and the serial interface is not used, it is better to connect the pull-up resistors directly to the AD7156 VDD.
Rev. 0 | Page 25 of 28
07726-058
AD7156
APPLICATION EXAMPLES
0.1F 1k 1k
VDD
CIN1 CSENS1 EXC1 CIN2 CSENS2 EXC2
AD7156
SDA SCL OUT1 OUT2 1k LED1 1k LED2 3V BATTERY
GND
Figure 49. AD7156 Standalone Operation Application Diagram
3.3V 0.1F 1k 1k
VDD
CIN1 CSENS1 EXC1 CIN2 CSENS2 EXC2
AD7156
SDA SCL SDA SCL
HOST MICROCONTROLLER
OUT1 OUT2
IRQ1 IRQ2
07726-059
GND
Figure 50. AD7156 Interfaced to a Host Microcontroller
07726-060
1k 0.1F VDD 39k CSENS1 82k 68pF 10k CIN1 22pF EXC1 47pF 39k CSENS2 82k 68pF 10k CIN2 22pF EXC2 47pF GND OUT2 10F
3.3V 1F
ADP1720-3.3
1F R1
VSUPPLY
AD7156
SDA SCL
1k
1k
R2
OUT1
OUT1
Q1
OUT2
Q2
07726-061
Figure 51. AD7156 Standalone Operation with EMC Protection
Rev. 0 | Page 26 of 28
AD7156 OUTLINE DIMENSIONS
3.00 BSC SQ 0.30 0.23 0.18
6 10 *EXPOSED PAD (BOTTOM VIEW)
0.50 BSC
PIN 1 INDEX AREA 0.50 0.40 0.30
TOP VIEW
1.74 1.64 1.49
5
1
0.80 0.75 0.70 SEATING PLANE
0.80 MAX 0.55 NOM
2.48 2.38 2.23 0.05 MAX 0.02 NOM
PIN 1 INDICATOR (R 0.20)
0.20 REF *FOR PROPER CONNECTION OF THE EXPOSED PAD PLEASE REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
031208-B
Figure 52. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7156BCPZ-REEL 1 AD7156BCPZ-REEL71 EVAL-AD7156EBZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] Evaluation Board
Package Option CP-10-9 CP-10-9
Branding C6L C6L
Z = RoHS Compliant Part.
Rev. 0 | Page 27 of 28
AD7156 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07726-0-10/08(0)
Rev. 0 | Page 28 of 28

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